Today’s Dimms Use What Size Data Path – Modern electronic devices such as mobile phones, tablets, cloud computing and networks require very high performance. Besides CPU speed/performance, memory plays a very important role in overall system performance. Double data rate (DDR) memories have become a common choice for designers in all complex devices due to their low latency, large storage size, and low power consumption.
Memory is a data storage device in electronic products. Stores processed information/data and provides it to the administrator upon request. At a high level, memory is classified into primary memory and secondary memory.
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Primary memory is further classified into random access memory (RAM) and read only memory (ROM). RAM is non-volatile memory and data will be lost after power off. ROM stores data even after the power is turned off. As VLSI technology has advanced, memory design, memory chip density, size, speed, and communication interface have been greatly improved.
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RAM is further classified into SRAM and SDRAM. SRAM is static RAM and SDRAM is synchronous dynamic RAM. The architectural difference between the two is that DRAM uses 1 transistor and 1 capacitor for each bit of memory, while SRAM uses 1 flip-flop (~6 transistors per flip-flop) to create one bit. SDRAM is slightly slower due to higher access time compared to SRAM. Since the size of the capacitor/transistor is smaller than that of the flip-flop, the memory density of SDRAM is higher compared to SRAM. SDRAM is dynamic storage because buffers tend to wear out over time, and if they are not refreshed frequently, SDRAM will not retain the stored data.
SRAM has become the default choice for cache memory because they are very fast and have very little access time. They are located inside the processor or can be connected externally. The cache acts as a buffer between the external RAM memory and the processor. This memory stores frequently used data/instructions and makes them immediately available to the processor when requested. In general, cache memory reduces the average time to access data from main memory.
As mentioned earlier, SDRAM stands for Synchronized Dynamic RAM, where the I/O, internal clock, and bus clock are synchronized. For example PC133 I/O, internal clock and bus clock are 133MHz. A single data rate means that SDR SDRAM can read/write only once per clock. The SDR SDRAM must wait for the previous command to complete before it can perform another read/write operation.
The demand for high data rates and high data density lead to the evolution of SDR into the concept of DDR. The demand for higher data rates and higher data density is driving the shift from SDR to DDR. In DDR SDRAM, data is latched on both edges—positive as well as negative edge—resulting in doubling the data transfer rate. Thus, DDR achieves greater bandwidth compared to SDR SDRAM; doubles the transfer speed without increasing the clock speed.
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Over the past few decades, many memory improvements have occurred in DDR technology. DDR has become very popular in the market and is widely used in notebook computers, laptops, servers and embedded computer systems. DDR offers many improvements such as increased processing speed, improved storage density, reduced power consumption, and added error detection features such as CRC, reducing SSN noise by implementing a bit-switching concept. In the next section, we will discuss the evolution of DDR memories and their advantages.
The first generation of DDR memory had a 2-bit prefetch buffer, twice that of SDR SDRAM. An internal clock frequency of 133 ~ 200MHz gives DDR1 transfer rates of 266 to 400 MT/s (million transfers per second). DDR1 ICs were released in 1998.
DDR2 works with an external data bus twice as fast as DDR1 SDRAM. This is achieved with an improved bus signal. The default DDR2 buffer is 4-bit, which is double that of DDR SDRAM. DDR2 memory has the same internal clock frequency (133~200 MHz) as DDR memory. However, DDR2 memory has improved transfer speed (533 ~ 800 MT/s) and I/O bus signal. DDR2-533 and DDR2-800 memory types were released in 2003.
DDR3 operates at twice the speed of DDR2. This is achieved by further improvements in the bus signal. The DDR3 prefetch buffer width is 8 bits, double that of DDR2. The transfer speed of DDR3 memory is 800 ~ 1600 MT/s. DDR3 operates at a lower voltage of 1.5V compared to DDR2’s 1.8V, resulting in 40% lower power consumption. DDR3 has two added features which are – ASR (Automatic Self Refresh) and SRT (Self Thermal Refresh).
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DDR4 operates at twice the speed of DDR3. DDR4 operates at low operating voltage (1.2 V) and high transfer rates. The transfer speed of DDR4 is 2133 ~ 3200MT/s. DDR4 adds a new technology with four banks. Each bank group has a one-handed operation feature. DDR4 can process 4 data cycles within a clock cycle, so the efficiency of DDR4 is better than DDR3. DDR4 has some additional features like DBI (data bus inversion), data bus CRC (circular inadequacy check) and command/address parity. These features can improve the signal integrity of DDR4 memory and improve data transfer/access stability. Independent programming of individual DRAM modules on DIMM modules allows better control of die-by-die completion.
DDR5 operates at twice the speed of DDR4. The transfer speed of DDR5 is 3200 ~ 6400 MT/s. DDR5 specifications were released in November 2018, and ICs are expected to be on the market by 2022.
The operating voltage VDD is changed from 1.2V to 1.1V, which reduces power consumption. On the other hand, a lower VDD means a smaller noise immunity margin.
With the addition of DDR5 DIMMs, power management moves from the motherboard to the DIMMs themselves. DDR5 DIMMs have a 12V power management IC that allows for better system load balancing and helps with signal integrity and noise issues.
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DDR4 DIMMs have a 72-bit bus consisting of 64 bits of data plus eight bits of ECC (Error Correction Code). In DDR5, each DIMM will have two 40-bit channels (32 data bits and 8 ECC bits). Although the data width is the same (64 bits in total), having two independent subchannels improves the efficiency of DDR memory access. The advantage of this is that higher MT/s are encouraged and are more efficient.
In DDR4, the RCD Registered Clock Driver (RCD) provides two output clocks on each side. The RCD in DDR5 provides 4 output clocks on each side, giving each channel an independent clock. This improves signal integrity and helps us deal with the low noise margin problem that occurs due to VDD reduction.
The packet length of DDR4 is eight, while for DDR5 the packet length will be extended to eight and sixteen to increase the packet charge. A packet length of 16 (BL16) allows one packet to reach 64 bytes of data. This results in a significant improvement in alignment and, in two ways, greater memory efficiency.
DDR5 buffer DIMMs allow system designers to use densities up to 64 Gb of DRAM in a single system package. DDR4 provides 16 Gb of DRAM in a single die package.
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In the following table, we have compared some important features of DDR RAM from different generations for better understanding.
The data transfer rate of DDR memory determines how fast programs will run. The importance of transfer speed becomes clear when you run several applications at the same time or a photography program. Memory transfer speed is determined by three factors such as the bus clock frequency, the type of transfer process, and the number of bits transferred.
The interface between the memory and the standard DDR4 processor is shown in the following figure. This interface contains group signals that include data, address, clock, and control signals.
The table below lists some of the basic and important signals used in data transfer between the CPU and SDRAM memory.
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The clock is a different sign. All address and control signals are sampled during the pose and clock edge crossings.
Data Bus is a single signal while Data Strobe is a discrete signal. Data is read or written to memory against the flash signal. It acts as a flag for valid data.
DDR memories are available with data bus widths such as DQ [0:3], DQ [0:7] and DQ [8:15]. In the case of DIMMs, the maximum total width of the data bus is 32 bits or 64 bits depending on the processor. In the DDR4 version, an additional 8 bits are allocated for error control, so the bus width becomes 40/72 bits.
DDR4 uses data bus switching to reduce switching noise at the same time, thus improving power noise and reducing IO power frequency. DBI# is an active low and bidirectional signal. During a write operation, if DBI# is sampled low, the DRAM inverts the write data received on the DQ inputs. If DBI# is high, the DRAM leaves the data received on the DQ inputs unchanged. During a read operation, the data read on its DQ output is reversed by the DRAM. The DBI# pin is driven
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